The invention relates to adapter devices, especially adapter devices for use in debugging.
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network, including for example connection to a host microcomputer for use in debugging routines. Such systems are also known in which each of the interconnected microcomputer chips has its own local memory. For speed of communication on on-chips it is common for bit packets to be transmitted between modules on a chip in a bit parallel format. However problems arise in both power consumption and available pin space in providing for external off-chip communications in the same parallel bit format as that used on-chip. Such microcomputers require access to instruction or code sequences and for efficient operation it is desirable for the instructions to be retrievable from locations within the address space of the CPU. One approach described in co-pending European patent application number 97308517.8 is to provide an on-chip external communication port forming part of the memory address space of the CPU from which instructions may be fetched and which translates between a parallel format on-chip and a less parallel format for off-chip communications. By itself, however, this approach does not address the following problem. When an external computer is linked to the external communication port, the performance of the system may be poor if a single communication protocol runs all the way from the chip to the external computer. This is because the on-chip protocol is typically a low-level protocol of a lower latency than the protocols that are most suitable for use at the external computer. Also, the on-chip protocol can be electrically fragile, and unreliable if run over greater lengths than around 1.5 m. This imposes a physical limitation on the debugger if the on-chip protocol is used all the way from the chip to the external computer.
According to the present invention there is provided an adapter device for assisting debugging of a microprocessor on a single integrated circuit chip, the integrated circuit chip comprising an on-chip CPU with a plurality of registers, a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU, and an external communication port connected to the said bus on the integrated circuit chip, the communication port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device comprising a first communication unit for connection to the communication port with the first external format; a second communication unit for connection to an external computer device with a second external format having a higher latency than the first external format; a second memory local to the adapter device; and a processing unit local to the adapter device and operable: (a) in a first mode to translate between the first external format and the second external format to allow the external computer device to communicate directly with the communication port; (b) in a second mode to connect the second communication unit to the second memory to allow the external computer device to access the second memory; and (c) in a third mode to execute instructions stored in the second memory to transmit data via the first communication unit to the communication port.
The communications port suitably forms part of the memory address space of the CPU. Then, the second memory preferably forms part of the address space allocated to the port. The adapter device preferably stores data specifying the mapping of the memory address space formed by the port on to the memory address space in the second memory. The external computer suitably has a third memory which forms part of the address space allocated to the port. Then the adapter device suitably stores data specifying the mapping of the memory address space formed by the port on to the memory address space in the third memory.
The adapter device may comprise a third communication unit for connection to a second external computer device with the second external format. The processing unit local to the adapter device is suitably operable to allow the second external computer device to communicate directly with the communication port.